1. Field of the Invention
The present invention relates to a method of manufacturing a thin-film transistor panel used for an active matrix liquid crystal display device.
2. Description of the Related Art
A thin-film transistor panel (hereinafter referred to as "TFT panel") is used for an active matrix liquid crystal display device. This TFT panel has a transparent substrate of glass or the like, on which gate lines, thin-film transistors (TFTs), pixel electrodes connected to the source electrodes of the associated TFTs, and data lines are provided.
FIGS. 7 and 8 are a cross-sectional view and a plan view of part of a conventional TFT panel, respectively. A gate line G1 and a TFT 2 are formed on a transparent substrate 1 of glass or the like.
The TFT 2 comprises a gate electrode Ga formed from the gate line G1, a gate insulating film 3 of SiN (silicon nitride) formed on the gate electrode Ga, an i-type semiconductor layer 4 of a-Si (amorphous silicon) formed opposite to the gate electrode Ga on the gate insulating film 3, n-type semiconductor layers 5 of a-Si, doped with n-type impurities and formed on the i-type semiconductor layer 4 with a channel region therebetween, and a source electrode So and a drain electrode Do both formed on the n-type semiconductor layers 5. The gate line G1 is formed of Al (aluminum), a low-resistance metal, or an Al base alloy consisting of Al and a high-melting point metal such as Ti (titanium). The source and drain electrodes So and Do are formed of metal, such as Cr (chromium), which provides a good ohmic contact to the n-type semiconductor layer 5.
A blocking insulating film 6 of SiN is formed on the channel region of the i-type semiconductor layer 4 to protect the i-type semiconductor layer 4 against any damage at the time etching is conducted to isolate the n-type semiconductor layer 5 in the channel region.
The gate insulating film (transparent film) 3 of the TFT 2 is formed nearly over the entire surface of the substrate 1, covering the whole gate line G1 except for its terminal portion. A pixel electrode 7 is formed on the gate insulating film 3. This pixel electrode 7, formed by a transparent conductive film of ITO or the like, has one end edge connected to the source electrode So of the TFT 2.
The data line D1, which is connected to the drain electrode Do of the TFT 2, is provided on an interlayer insulating film 8 of SiN, which is so formed as to cover the TFT 2 and pixel electrode 7. This data line D1 is coupled to the drain electrode Do through a contact hole 9 formed in the interlayer insulating film 8. Like the gate line G1, the data line D1 is formed of Al, a low-resistance metal, or an Al base alloy. Reference numeral "10" denotes an overcoat insulating film of SiN.
The above TFT panel is manufactured through the following processes. The gate line G1, TFT 2 and pixel electrode 7 are formed on the substrate 1 by a well-known method. The interlayer insulating film (SiN film) 8 is then deposited on the resultant structure by a plasma CVD apparatus. After the contact hole 9 is formed in this interlayer insulating film 8 using a photolithography technique, a metal film (Al or Al base alloy film) for a data line is deposited on the interlayer insulating film 8 by a sputtering apparatus. Then, this data line metal film is patterned using a photolithography technique to form the data line D1. Finally, the overcoat insulating film (SiN film) 10 is deposited on the resultant structure by the plasma CVD apparatus.
In this TFT panel manufacturing method, as the TFT 2 and pixel electrode 7 formed on the substrate 1 are covered with the interlayer insulating film 8 on which the data line D1 is formed, even if the data line D1 is formed of Al or Al base alloy, the pixel electrode 7 will not be damaged at the time a resist mask is formed for patterning the data line metal film.
While a metal film of Al or Al base alloy has a low resistance and good conductivity, it is likely to have pin holes.
It is know that a resist mask is formed by coating a photoresist on the data line metal film and then subjecting this photoresist to exposure and developing processes. In this case, if the data line metal film is an Al film or Al base alloy film having pin holes, a developer solution penetrates through those pin holes to the back of this metal film at the time the photoresist is developed.
The developer solution is an electrolytic solution. If the pixel electrode 7 is in direct contact with the data line metal film, therefore, the electrolytic effect of the developer solution that has penetrated through the pin holes of the data line metal film causes a cell reaction between the pixel electrode 7 of ITO or the like and this metal film of Al or Al base alloy. This would cause a melt defect on the pixel electrode 7 of ITO or the like, or would result in separation of the pixel electrode 7 from the gate insulating film 3.
When the TFT 2 and pixel electrode 7 formed on the substrate 1 are covered with the interlayer insulating film 8 and the data line D1 is formed on the insulating film 8 as mentioned above, even if the data line D1 is an Al or Al base alloy film having pin holes and the developer solution penetrates through those pin holes, no cell reaction would occur between the pixel electrode 7 and the data line metal film. Therefore, the pixel electrode 7 will not be damaged at the time a resist mask is formed on the data line metal film.
But, the conventional method requires the deposition of the interlayer insulating film 8 on the substrate 1 to cover the TFT 2 and pixel electrode 7. As mentioned above, the interlayer insulating film (SiN film) 8 is formed by a plasma CVD apparatus. This film deposition by the plasma CVD apparatus takes time, thus resulting in a poor performance of manufacturing a TFT panel. In addition, this plasma CVD apparatus is large and expensive, so that the production equipment becomes large and a large amount of cost is required accordingly.